1. Technical Field
This disclosure relates to a sense amplifier flip flop and, more particularly, to a sense amplifier flip flop which adjusts an offset.
2. Description of the Related Art
A system which performs an input or output operation at high speeds has many important parts. However, an input/output portion is one of the parts which critically affect a performance of the system. Among such an input/output portion, a flip flop exactly receives an input signal and samples it.
A semiconductor memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) includes a data input buffer which detects an externally input data signal and buffers it at a predetermined level for matching logic levels within its memory cells and a latch which continuously maintains data input from an external portion until the data is transmitted to the memory cell.
FIG. 1 is a circuit diagram illustrating a first conventional sense amplifier flip flop. A pre-charging portion 10 includes a PMOS transistor P1 connected between a power voltage Vdd and a first node Node1 and a PMOS transistor P2 connected between a power voltage Vdd and a second node Node2. The PMOS transistors P1 and P2 receive a clock signal CLK through their gates and are turned on to pre-charge the first and second nodes Node1 and Node2 when the clock signal CLK having a low level is applied, respectively.
A differential input portion 20 includes an NMOS transistor N1 which is connected between a common node NodeC and a ground voltage Vss and serves as a switch for driving the differential input portion 20 in response to the clock signal CLK, an NMOS transistor N2 connected between a third node Node3 and the common node NodeC to receive an input signal D, and an NMOS transistor N3 connected between a fourth node Node4 and the common node NodeC to receive an inverted input signal DB. When the clock signal having a high level is applied, the NMOS transistor N1 is turned on, so that the differential input portion 20 receives the input signal D and the inverted input signal DB, respectively, through the NMOS transistors N2 and N3 to detect a voltage difference between the input signal D and the inverted input signal DB.
A differential amplifying portion 30 includes two inverters, i.e., first and second inverters 30-1 and 30-2 respectively connected between the power voltage Vdd and the third and fourth nodes Node3 and Node4. An input of the first inverter 30-1 is connected to the node Node2, and an input of the second inverter 30-2 is connected to the first node Node1.
The differential amplifying portion 30 amplifies the voltage difference between the input signal D and the inverted input signal DB, detected by the differential input portion 20, to output a differential signal Mout and an inverted differential signal MoutB respectively to the first and second nodes Node1 and Node2.
A latch portion 40 includes two NAND gates 40-1 and 40-2. The first NAND gate 40-1 receives the differential signal Mout and an inverted output signal QB, i.e., an output of the second NAND gate 40-2 to output an output signal Q, and the second NAND gate 40-2 receives the inverted differential signal MoutB and an output signal Q, i.e., an output of the first NAND gate 40-1 to output an inverted output signal QB.
The latch portion 40 latches the differential signal Mout and the inverted differential signal MoutB as an SR latch to output the output signal Q and the inverted output signal QB.
TABLE 1CLK(L)DMoutMoutBQX11HoldCLK(H)H010L101
Table 1 is a truth table of the sense amplifier flip flop of FIG. 1. An operation of the sense amplifier flip flop is described below with reference to FIG. 1 and Table 1. When the clock signal CLK having a low level is applied, the PMOS transistors P1 and P2 of the pre-charging portion 10 are turned on, and the NMOS transistor N1 of the differential input portion 20 is turned off. As a result, the power voltage Vdd is applied to the first and second nodes Node1 and Node2, and the differential signal Mout and the inverted differential signal MoutB, each having a high level are applied to the latch portion 40. The latch portion 40 by the nature of the SR latch maintains the output signal Q and the inverted output signal QB “as is” in a previous state when the differential signal Mout and the inverted differential signal MoutB both have a high level. At the same time, the pre-charging portion 10 pre-charges the first and second nodes Node1 and Node2.
When the clock signal CLK having a high level is applied, the PMOS transistors P1 and P2 of the pre-charging portion 10 are turned off, and the NMOS transistor N1 of the differential input portion 20 is turned on.
When the input signal D having a high level is applied to the differential input portion 20, the NMOS transistor N2, which receives the input signal D, is turned on, and the NMOS transistor N3, which receives the inverted input signal DB, is turned off.
When the NMOS transistor N2 of the differential input portion 20 is turned on, since the first and second nodes Node1 and Node2 have been pre-charged, the NMOS transistor N4 of the first inverter 30-1 of the differential amplifying portion 30 is also turned on. As a result, a voltage level of the first node Node1 is lowered. When the voltage level of the first node Node1 is lowered, the PMOS transistor P3 is turned off. As a result, the differential signal Mout transitions to a low level, and is output to the latch portion 40.
In contrast, the NMOS transistor N3 of the differential input portion 20 and the NMOS transistor N5 of the second inverter 30-2 are turned off, and the PMOS transistor P4 is turned on. As a result, the second node Node2 is maintained at a pre-charged voltage level, and the inverted differential signal MoutB transitions to a high level and is output to the latch portion 40.
The latch portion 40 outputs the output signal Q having a low level and the inverted output signal QB having a high level when the differential signal Mout transitions to a low level and the inverted differential signal MoutB transitions to a high level.
When the input signal D having a low level is applied to the differential input portion 20, the NMOS transistor N2, which receives the input signal D, is turned off, and the NMOS transistor N3, which receives the inverted input signal DB, is turned on.
When the NMOS transistor N3 of the differential input portion 20 is turned on, since the first and second nodes Node1 and Node2 have been pre-charged, the NMOS transistor N5 of the second inverter 30-2 of the differential amplifying portion 30 is also turned on. As a result a voltage level of the second node Node2 is lowered. When the voltage level of the second node Node2 is lowered, the PMOS transistor P4 is turned off, so that the inverted differential signal MoutB transitions to a low level and then is output to the latch portion 40.
In contrast, the NMOS transistor N2 of the differential input portion 20 and the NMOS transistor N4 of the first inverter 30-1 are turned off, and the PMOS transistor P3 is turned on. As a result, the first node Node1 is maintained at the pre-charged voltage level, and the differential signal Mout transitions to a high level and is output to the latch portion 40.
The latch portion 40 outputs the output signal Q having a high level and the inverted output signal QB having a low level when the differential signal Mout transitions to a high level and the inverted differential signal MoutB transitions to a low level.
That is, the first and second inverters 30-1 and 30-2 of the differential amplifying portion 30 are connected such that the inputs crosses the outputs of the other inverter and thus amplify and output a small voltage difference applied from the differential input portion 20.
The sense amplifier flip flop of FIG. 1 has a structure including a master including the pre-charging portion 10, the differential input portion 20, and the differential amplifying portion 30 and a slave latch including of the latch portion 40. There is an advantage in that the master is configured in the form of a differential amplifier and is capable of handling a signal level having small magnitude, and the slave latch can perform a stable high speed operation and thus can process an input signal level having small magnitude at a high speed.
However, there is a disadvantage in that a voltage offset may occur as well. Such an offset may occur as a result of a processing error, a layout error, or mismatching of a threshold voltage Vth in the NMOS transistor.
FIG. 2 is a circuit diagram illustrating a second conventional sense amplifier flip flop. The sense amplifier flip flop of FIG. 2 includes multiple capacitors as a solution for resolving the offset problem. Capacitors C11 to C13 and C21 to C23 are respectively connected to the third and fourth nodes Node3 and Node4 to control an electric current which flowing from the differential amplifying portion 30 to the differential input portion 22 to thereby adjust the offset.
When the input signal D and the inverted input signal DB each have a high level, there should be no voltage difference between the two signals D and DB. As a result, there should be no difference in the electric current which flows from the NMOS transistor N4 through the third node Node3 as compared with the electric current which flows from the NMOS transistor N3 through the fourth node Node4.
However, if it is assumed that an electric current I+Ioffset which flows through the fourth node Node4 is greater than an electric current I which flows through the third node Node3 by the offset current Ioffset, the offset current Ioffset is a cause of errors when the input signal is determined and thus should be offset.
To this end, a predetermined number of capacitors among the capacitors C21 to C23 are connected to the fourth node Node4, enough to offset the offset current Ioffset from the current I+Ioffset which flows through the fourth node Node4. The remaining capacitor(s) and the capacitors C11 to C13 connected to the third node Node3 are disconnected by fuse cutting. For example, if the offset current offset is offset by the capacitor 21, the remaining capacitors C11 to C13, C22, and C23 are disconnected by fuse cutting.
FIG. 3 is a circuit diagram illustrating a third conventional sense amplifier flip flop. In FIG. 3, as a method for resolving the offset problem, NMOS transistors N2, N21, N22, N3, N31, and N32 are arranged in the differential input portion 24.
The sense amplifier flip flop of FIG. 2 reduces the offset current Ioffset to adjust the offset, whereas the sense amplifier flip flop of FIG. 3 allows the current I flowing through the third node Node3 to increase by the offset current Ioffset to adjust the offset.
If it is assumed that an electric current I+Ioffset, which flows through the fourth node Node4, flows by the offset current Ioffset more than an electric current (I), which flows through the third node Node3, as in FIG. 2, a predetermined number of NMOS transistors are remain connected to allow a greater electric current to flow to the NMOS transistor N2 side connected to the third node Node3. The remaining NMOS transistors are disconnected by fuse cutting.
For example, if an additional electric current that is as much as the offset current Ioffset flows to the third node Node3 due to the NMOS transistor N21, the remaining transistors N22, N31, and N32 are disconnected by fuse cutting.
Similarly to the circuit of FIG. 3, If it is assumed that an electric current I+Ioffset, which flows through the fourth node Node4, flows by the offset current Ioffset more than an electric current (I), which flows through the third node Node3, it is possible to make an electric current flow more to the NMOS transistor N2 side by increasing the size of the NMOS transistor N2.
Unfortunately, in adjusting the offset of the sense amplifier flip flops shown in FIGS. 2 and 3, multiple capacitors or transistors are required, and thus there is a disadvantage in that it is not easy to design and the layout area size of the sense amplifier flip flop is increased. In addition, a process for blowing off the fuses to adjust the offset is needed.